Does UVM contains any program block?

UVM
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Hi all,

we were analyzing UVM library and have following question.
As per our understanding, system verilog testcase is recommended to write inside program block or entire class hierarchy should be start/invoke from program block. As program block is performing all timing events in Reactive region queue, which will help to avoid Race condition between design and testbench.
Now, in UVM what will take care of this? Does entire hierarchy start from module only, as run_test() is called from module? if yes, how Race condition will be taken care?

Thanks and Regards,
Mitesh Patel

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In reply to mitesh.patel:

The SV program construct does not allow to instantiate inside any component. For this reason it is not the best choice for strting the test you want to execute. Instead use a top level module instantiating there your DUT, the SV interface and the test class.
Race conditions can be avoided by using clocing blocks or inserting special logic.

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In reply to mitesh.patel:

Read Dave’s article about program blocks.

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In reply to cgales:

Thanks chr_sue and cgales, for your response.