we were analyzing UVM library and have following question.
As per our understanding, system verilog testcase is recommended to write inside program block or entire class hierarchy should be start/invoke from program block. As program block is performing all timing events in Reactive region queue, which will help to avoid Race condition between design and testbench.
Now, in UVM what will take care of this? Does entire hierarchy start from module only, as run_test() is called from module? if yes, how Race condition will be taken care?
Thanks and Regards,