Based on system verilog event regions, testbench code is expected to be run in reactive region to avoid race conditions. In that case is the UVM Code which drives data to testbench runs in reactive region?
In reply to Mani KIran:
This is not correct. You need to start your UVM testbench in a program block to get into the reactive region, and you rarely see anyone do that. Please see http://go.mentor.com/programblocks