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  • Does Not Cover one of same two assertion?

Does Not Cover one of same two assertion?

UVM 6753
#coverage 8 assertion 6 #systemverilog 102 test 2 #uvm 278
nrllhclb
nrllhclb
Full Access
9 posts
January 30, 2019 at 3:10 am

Hi,

I wrote two assertion in same way, but one of them is covered, but other does not.

(a_signal == 16'h48) ##[1:6] $fell(c_signal) |=> it is ok

(a_signal == 16'h28) ##[1:6] $fell(c_signal) |=> does not work

I observed test's graphic that two cases (16'h48 and 16'h28) occur. but the one of assertion doesnt cover.

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chr_sue
chr_sue
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3893 posts
January 30, 2019 at 7:43 am

In reply to nrllhclb:

You are showing only the pre-conditions. But we do not see what should happen after the pre-condition was met.

dave_59
dave_59
Forum Moderator
10908 posts
January 30, 2019 at 8:13 am

In reply to nrllhclb:

What you show are sequences, not complete assertions.

— Dave Rich, Verification Architect, Siemens EDA

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