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  • does it make sense to have array of analysis implementations?

does it make sense to have array of analysis implementations?

UVM 7030
UVM array analysis imp 1
victorh
victorh
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4 posts
April 23, 2023 at 3:22 pm

I have a design that has a repeated smaller block and the repetition is parameterized.
In the UVM environment, it is easy to control the number of (agents, monitors, ... ) in build and connect phases, but when it comes to the scoreboard there is a problem in using array of analysis implementations since we cannot have an array of write functions and each analysis implementation is connected to one write function by default.

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dave_59
dave_59
Forum Moderator
11451 posts
April 24, 2023 at 9:08 am

In reply to victorh:

I do not understand where you think there is a problem. An analysis_port is designed to broadcast to multiple analysis implementations.

— Dave Rich, Verification Architect, Siemens EDA

victorh
victorh
Full Access
4 posts
May 03, 2023 at 12:44 pm

In reply to dave_59:

The problem is defining different write functions for each analysis implementation if they are written as array.
I know an analysis port can connect to multiple analysis implementations and even that that is not needed because in this example, we have an array of analysis ports and an array of analysis implementations so each port is connected to one implementation. The problem is in the write functions.

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