Does the constraint in `uvm_do_with will override the constraint in the item class?

I’m confuse whether the constraint in uvm_do_with will override the constraint in the item class. Can somebody confirm this? Which constraint has a higher priority? Is it the one in the item class or the one in the uvm_do_with?
What is actually happening when constraints are added in `uvm_do_with? Is it just adding another constraint block inside the item class?

It is highly recommended NOT to use the `uvm_do_* macros. The macros remove some of the control that the user might want such as object handle reuse, constraint manipulation and direct variable assignment. The user should just use the standard methods for creating, randomizing and sending sequence items.

The answer to your question comes from the SystemVerilog LRM. If you don’t have a copy, it is available for free.

18.7 In-line constraints — randomize() with
By using the randomize() with construct, users can declare in-line constraints at the point where the randomize() method is called. These additional constraints are applied along with the object constraints.

In reply to Reuben:

Hi Ruben,
Did you find any solutions to this question ?
I seem to doubt if `uvm_do_with can override existing constraints in the class.

In reply to Reuben:

I’m confuse whether the constraint in uvm_do_with will override the constraint in the item class. Can somebody confirm this? Which constraint has a higher priority? Is it the one in the item class or the one in the uvm_do_with?
What is actually happening when constraints are added in `uvm_do_with? Is it just adding another constraint block inside the item class?

If you have constraints in your seq_item defined the inline constraint from the sequence are considering these constraints together with the constraints from the seq_item definition.
Constraints can be overriden when using the same names for the constraints. This is a SV feature.