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  • Disabling phases for child components

Disabling phases for child components

UVM 7028
kp
kp
Forum Access
6 posts
October 25, 2022 at 2:33 pm

Hi,

We have following TB structure
env.sv : instantiates class A, B, C (uvm_components)

All phases are called for env.sv
Is there a way to call build and connect phases for A,B,C but skip the rest of the phases?

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cgales
cgales
Forum Moderator
2118 posts
October 26, 2022 at 5:14 am

In reply to kp:

Can you explain why you want to not call all phases for the sub-components?

If you don't add code to the component for a specific phase, the empty phase in the base class will be used.

kp
kp
Forum Access
6 posts
October 26, 2022 at 8:55 am

In reply to cgales:

I am trying to reuse components A,B,C between two different environments
- one is fully UVM based wherein we want all phases to get called for A,B,C
- the other one is semi-UVM. Here the run_phase is implemented in C by a top layer and we want to bypass all phases after connect_phase for A,B,C and their children

dave_59
dave_59
Forum Moderator
11444 posts
October 27, 2022 at 12:11 am

In reply to kp:

You need to provide a few more details. What do you mean by "bypass/skip". In UVM terms if you get to the end of all phases, the simulation terminates. Are there other components D,E,F that are running their phases? How will the C code let those other components know it is done with the run_phase.

This seems like an XY Problem.

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