Different Read write agents accessing same registers

UVM
,
1

In my verification environment I have RAL model for registers available in RTL.
However unfortunately we have two separate agents making read/write access via single interface. Since I am ONLY consumer, I couldn’t touch separate agents. (Else I would have kept only one agent, catering for both read/write).

Now as expected while setting sequencer for register map, I am ONLY able to set either of read/write agent’s sequencer i.e.


my_reg_block.reg_map.set_sequencer(wt_agent.sequencer, my_adapater);
//my_reg_block.reg_map.set_sequencer(rd_agent.sequencer, my_adapater);

Any suggested way to circumvent the issue?

Also, is it possible to achieve set_sequencer from sequence, when we actually know whether it’s a read or write sequence.
Any help will appreciate.
Thanks.

2

In reply to bhupesh.paliwal:

Why don’t you:

  1. write “virtual sequencer”, it has 2 sequencers: wr_sequencer, rd_sequencer. You point these sequencer to wr_agent.sequencer and rd_agent.sequencer respectively. And set this “virtual sequencer” to reg_map.
  2. Find the way to capture transaction from reg_block in “virtual sequencer”, identify type of transaction which is write or read. According to type of transaction, you pass to wr_sequencer or rd_sequencer respectively.

The sequencer provides you a task “execute_item” that pass directly transaction to.

This is totally an idea. I haven’t implemented it yet.

3

In reply to chrisle:

Your proposal looks nice, but it is less than a workaround and might solve the problem. But it is only gambling around a bad environment. The problem shows how important is a well architected environment. A few months ago we had the discussion about the problem with different agents for READ and WRITE and the questioner was insisting on this architecture. Now we can see the limitations.