Differences between Sequence item, Sequence, Transaction, Test

UVM
1

Hi,
I am very much new in UVM. I am trying to understand some of the terminology. I checked the cookbook, but still have the confusion. I am writing down my conclusion, please correct me.

  1. Sequence item: It’s a individual transaction, such as only read, or only write. Transaction is known as Sequence item in UVM.
  2. Sequences: It’s a collection of sequence items, such as read, write.
  3. Test: There are two test in my understanding in uvm, sequence sometimes called as Test, since it do a particular set of operation. And other
    Test is what Instantiate the environment, and further agents etc.
    (Now what test is called as what test officially to avoid the confusion?)

I would really appreciate if anyone can explain me these terminology.

Regards,
Pankaj

2

In reply to papatel:

To correct you
(1) a sequence item is a transient object which contains data members and methods.
(2) a sequence is also a transient object which creates seq_items or executes other sequences,
(3) the test is a componnet which belongs to the UVM topology. It executes one or more sequences to verify certain DUT functionality. It can be configured with respect to the fuctionality.

3

In reply to chr_sue:
Hi chr_sue,

So
1.sequence_item are just a class having data members and methods, method can have both read and write (for example)?
2.Sequence are constructor for sequence_item?
3.A sequence can be replaced for test in common saying?

Regards,
Pankaj

4

In reply to papatel:

Yes a sequence item is a class. But it is a transient obejct. This will be cerated at any time and destroyed after ist has been processed.
A sequence is an extension of the seq_item. It is also transient. It describes how the sequence items will be generated.
A sequence and the test are completely different things. A test is a component object. It is created at runtime 0 and exists until the simulation hes been finished. In the test you can start 1 or more sequences. A component belongs to the testbench topology.

5

In reply to chr_sue:

So a sequence_item will define only methods, but sequence will defines ordering of those methods? Is that correct understanding?

Regards,
Pankaj

6
  1. A sequence_item is a transaction that is sent from a sequence to driver. The sequencER handles arbitration between the sequence/driver pair, especially then a sequence or multiple sequences are sending concurrent sequence_items to the driver.
  2. A sequence is the UVM’s implementation of the functor design pattern. Basically a functor is a class whose sole purpose is act like a pointer to procedure. In the UVM, this is the body() method of a sequence. This lets you build a library of sequences that can be selected through a variety of means. A sequence can call more sequences creating a hierarchy in the call stack. At some point lowest level sequence sends a sequence_item to the driver.
  3. From the UVM’s point of view, the “test” is the top level component that chooses the testbench architecture and top-level sequence. In many cases, there is a one-to-one correspondence between each top-level test and each top-level sequence, but there is no requirement for it to be that way.

In reply to papatel:

7

In reply to dave_59:

Hi Dave,
Suppose we have following transactions, all these are method written different in sequence_item.
1.Read 2.Write 3.Reset 4.Add
(Sequence_item1) (Sequence_item2) (Sequence_item3) (Sequence_item4)

So sequence can be, combination of any of the above, such as (1,2) or (2,3), which will first construct them, then bundle it so as to call them as sequence1, sequence2. and then will be feeded to driver through sequencer, and sequencer can send sequence2 first and sequence1 (arbitrate). Is it correct understanding now?

Regards,
Pankaj