Difference in using type_id::create() in constructor function new() and build_phase()

UVM
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1

Hi All,

I have a query on type_id::create(). I would like to know the difference between the usage of type_id::create() in the constructor function new() and in the build_phase(). I am familiar with type_id::create()in other phases(), "factory override" concepts and all.. but not able to get much info of using type_id in between new() and build_phase().  Even though it doesn't affect my project for now. I would like to know the major differences (if any) and where it may affect. please let me know if I am missing any concept here. here is the sample code


 virtual class sinc_base_test extends uvm_test;

   sinc_env env;         // Instantiate testbench environment
   sinc_tb_env_cfg cfg;  // Instantiate testbench configuration class

   // No UVM component utility macros because this is a virtual class
   // Constructor
   function new(string name, uvm_component parent = null);
      super.new(name, parent);
      cfg = sinc_tb_env_cfg::type_id::create("cfg"); // Create the configuration class
   endfunction : new

   // Build phase
   virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      ...
      
      // Create the testbench
        env = sinc_tb_env::type_id::create("env", this);
     // ***cfg = sinc_tb_env_cfg::type_id::create("cfg",this);*** 
     ...
     
   endfunction : build_phase

Thanks in advance,
Raghu krishna

2

In reply to raghu.krishnas:

Calling the create method in different functions generates only confusion. If this is your objective you can do this.
UVM is phased approach with dedicated tasks you should do in each phase.

3

In reply to raghu.krishnas:

There is no functional difference between calling create in the constructor new() or the build_phase() with the code you have shown.

The difference comes into play when extending the class sinc_base_test. SystemVerilog requires you to call super.new() as the first statement of the extended class’s new(). When you extend the build_phase(), there is no requirement to call super.build_phase(), and if you do, you can call it anywhere. This gives you much more flexibility when extending a class. So the UVM recommends putting all statements in the build_phase() when possible instead of new().

4

In reply to chr_sue:

In reply to raghu.krishnas:
Calling the create method in different functions generates only confusion. If this is your objective you can do this.
UVM is phased approach with dedicated tasks you should do in each phase.

Thanks Chr_sue. I do agree UVM is phased approach with dedicated tasks. I am familiar with create usage in phases. I would like to know the whether the create in constructor function instead of build_phase() would affect anywhere like factory, hierarchical issues or any other.

5

In reply to dave_59:

In reply to raghu.krishnas:
There is no functional difference between calling create in the constructor new() or the build_phase() with the code you have shown.
The difference comes into play when extending the class sinc_base_test. SystemVerilog requires you to call super.new() as the first statement of the extended class’s new(). When you extend the build_phase(), there is no requirement to call super.build_phase(), and if you do, you can call it anywhere. This gives you much more flexibility when extending a class. So the UVM recommends putting all statements in the build_phase() when possible instead of new().

Hi Dave
Thank you so much for your answer. Now I got the clear view.