Difference between uvm_put_port and uvm_nonblocking_put_port

UVM
1

Hi

What is the exact difference between a uvm_put_port and a uvm_nonblocking_put_port?

With a uvm_put_port , Should we implement try put and can_put as well?

Thanks
venkatesh

2

In reply to Venkatesh Maddibande Sheshadrivasan:

In general TLM, “ports” are requirements that they get connected to implementations with a specific set of callable methods.

uvm_nonblocking_put port requires the try_put() and can_put() methods.
uvm_blocking_put port requires the put() method.
uvm_put port requires all of the above.

You get an error if you try to call a method that was not specified by the port.

3

In reply to dave_59:

Thanks Dave ! Thats a very clear explanation

A follow up question , Lets say we connect 2 put_imp (components A and B) to a single port (component C whose max connection is 2)

When C send a transaction
Is there any deterministic way of knowing which of A and B 's implementation is triggered?

Thanks
Venkatesh

4

In reply to Venkatesh Maddibande Sheshadrivasan:

You could set up a field in your transaction to communicate that information.

5

Hi dave
is there any specific website other than chip verify,vlsi verify or verification guide… where we can get each and every information about uvm in one site only? If there is so please suggest.

6

In reply to Susheela:

https://verificationacademy.com/cookbook/uvm