Difference between has_reset and reset in uvm_reg_field class

in uvm_reg_field class configure method in input argument we pass has_reset and reset value. can any one explain me what is exact meaning of that.

extern function void configure(uvm_reg parent,
int unsigned size,
int unsigned lsb_pos,
string access,
bit volatile,
uvm_reg_data_t reset,
bit has_reset,
bit is_rand,
bit individually_accessible);

In reply to zalak patel:

If has_reset is set to 1. then the field is initialized to a default value (i.e, reset) that it takes when the testbench/design is in the reset state, i.e, when reset is high/low depending on your design.
It is natural and normal that registers in a design have reset values.

thanks for the reply.

but i want to know about what is the exact difference between uvm_reg_data_t reset and
bit has_reset in uvm_reg_field class, and what is exact application of it.

In reply to zalak patel:

It is plenty clear from my response what the difference is. Look up uvm bcl code for rest of the internals.