I have been assigned a task to develop a VIP for Watchdog timer keeping in mind that this particular could be reused on any SoC where low peripherals are accessed by any protocol (Like APB or any other).
For the reference we have ARM Watchdog Module (SP805) reference manual which actually uses APB interface for writing and reading of Watchdog timer (WDT) Registers.
The VIP architecture I came up with had two agents which sit on each different interface [one deal with APB related signal and another deal with WDT related signals]. If protocol changes than replace APB agent with protocol specific agent (that's the Idea).
Question I have are :
1) Is the architecture good enough to go ahead with?
2) Majority of functional checking is performed by assertions as we will be dealing with registers. Is that good enough or any other method would be required.
One of the Assertion code
checker wdt_assert_check (input logic paddr,pwdata,prdata,WDOGCLK,WDOGRESn,WDOGRES,WDOGINT);
logic bit dis_intr=(paddr==32'h00000008 && pwdata==32'h00000000||paddr==32'h00000008 && pwdata==32'h00000002); //if control reg is 00 or 02 it means interrupt is disabled
logic bit dis_res=(paddr==32'h00000008 && pwdata==32'h00000001||paddr==32'h00000008 && pwdata==32'h00000000); //if control reg is 00 or 01 it means reset is disabled.
int v; //local variable for down counter
logic [31:0]delay=pwdata; // loading data value as load register
((paddr==32'h00000000 && pwdata), v=delay+1'b1) |-> ((v>0,v=v-1'b1) [*0:$] ##1 v==0 ##1 (WDOGINT)); //when in load register some data is written than counter decrements until 0 and Interrupt is generated.
endchecker : wdt_assert_check
assert_wdt_int_gen: assert property (@(posedge WDOGCLK) disable iff (WDOGRESn||dis_intr) wdt_int_gen);
will this assertion work?
Its a checker file i am planning to bind to the top but i dont find it reusable with other protocols apart from APB.
3. I have implemented RAL model for WDT, at what level can it be used for behavior checking/can it add on some features to VIP.