Delays in between the write and read transaction

UVM
,
1

Hai folks,

I want to give delays in between the write transaction and read transaction.
writes and reads will perform simultaneously but while writing or reading I want to add gaps, how can I give could any give me an idea.

repeat(2) @(posedge clk) // will this work

2

In reply to Vickyvinayk:

https://verificationacademy.com/forums/uvm/add-clock-delay-sequence-using-existing-interface-clock-signal-present-interface.#reply-67700