Defines in arguments

UVM
1

Hi,
define ADDR_1 'h400 define ADDR_2 'h6000
class seq extends from base_seq;
////all constructors
task body()
register_wr(`ADDR_1);
endtask
endclass

class base_seq extends from uvm_sequence;

task register_wr()/////how can i get the defined value in base class can you please tell
addr = 'ADDR_1; //// if i call directly with out argument will it work, can you please tell me how to do it
endtask

endclass

2

In reply to srikanth.verification:

I don’t really understand your question. define macros are just text replacement and don't have any knowledge of SystemVerilog syntax. Perhaps your problem is more to do with compilation order. If that's the case it's better to put parameters in a package and import them rather than trying to use define macros.