Define heirarchy

UVM
,
1

Is it allowed by rules to use `define from uvm_env_cfg to top module

 //------------------EXAMPLE------------------//

//
 macro.svh (file_inside)
`define EC env_cfg
//


class env_cfg
rand bit [4:0] block_length;
endclass


module top

/*DEBUG*/ rd_dat_err_ = (1 + ((cmd_out_index == 21) ? 128 : **`EC.block_length**) + rd_dat_crc);

endmodule

now as you know the heirarchy of uvm initialization that top comes first and env comes later and this is

i have put the `EC.block_length in the top module for debugging purpose and that is originating from Env_cfg

so here my question is that, IS IT ALLOWABLE that i go ahead with this coding structure ?

2

In reply to milin parekh:

`define EC env_cfg
EC is the name of class, please point to the instance, it will work

3

In reply to saravanan_mobi:

I believe it is only useful to have a define to an object and not to a class definition.
And I do not see why you want to use this macro. If you need this you could make in the inital block of your toplevel an object of your cfg class and randomize it. Then you have specific value you can access.

4

In reply to milin parekh:

`define just defines text replacement by a preprocessor before it gets to SystemVerilog compilation. The code after replacing the macro text must be legal syntax, which yours is not.