Declaring a uvm_report_server class

While going over an example in EDAPlayground (UTB C - verificationguide.com - EDA Playground), I noticed that in the report_phase of the base test the uvm_report_server class is declared before the super function is called.


uvm_report_server svr
super.report_phase(phase);

I tried declaring the uvm_report_server after the super function but I see an error. I think this is something fundamental to UVM. Can someone please explain why should the uvm_report_server be declared before the super function gets called?

In reply to tpan:

This is a SystemVerilog language syntax requirement. Local variable declarations must come before any procedural statements within a block of code. The call to
super.report_phase(phase);
is a procedural statement, so the declaration of
svr
must come before it. (BTW, this comes from the Pascal Programming Language which the procedural part of Verilog is derived from)

Thanks Dave. It’s an interesting feature that you pointed out here. I have used UVM quite a bit but never realized it. I guess I have always had my variables declared globally in the class. So am I right in saying that even the below piece of code would result in a similar error -


...
super.main_phase(phase);
int a;
...

In reply to tpan:

Thanks Dave. It’s an interesting feature that you pointed out here. I have used UVM quite a bit but never realized it. I guess I have always had my variables declared globally in the class. So am I right in saying that even the below piece of code would result in a similar error -


...
super.main_phase(phase);
int a;
...

Yes