We have a UVM testbench and we have a DUT whose behavior can be configured through the content of its NVM. So far we leveraged some Verilog components to organize the NVM so that we can expose various configurations.
Unfortunately this mechanism is quite awkward since we need to pass information from our test to the verilog component, as well as to the rest of the agents and reference models to verify the correct behavior.
Now I have the impression that we should be using a different UVM infrastructure to configure the NVM and I’m considering switching to uvm_mem although I do not have any experience with it.
The main reason for switching is that currently is extremely difficult to do two specific things: randomize the content and collect coverage. So we are basically stuck with only checking few combinations of the configuration space, which often leads to escapes.
What is your take on uvm_mem and is it worth the effort? Do you have any good source to start using it?