Hello,
I am facing some problems implementing an explicit predictor for a UVM register model.
First of all, I considered using the standard uvm_reg_predictor. However, this does not fit my needs, since its structure is monolithic and dictates the use of an adapter.
As I may have more than 1 bus transaction for every register access, I think it is not suitable.
So I considered writing a custom predictor, but I have some concerns.
-
stimuli-based checks (i.e. mirror()) will no more be possible, since with the explicit predictor, the predict() and the check() are done in 2 different components, and I may end up having race conditions.
-
uvm_reg_predictor takes care of both checks and prediction, but for some registers I may want to bypass one or both.
For example, I want to bypass checks on volatile registers, and predictions on registers that are predicted by other specific components.
To disable checks, I see that I can use set_compare(UVM_NO_CHECK).
To selectively turn off prediction on some registers (and possibly turn it on again later) I see no predefined function, and I was thinking of
implementing my own.
Is my understanding correct? Am I missing something?
Thanks in advance for your help,
Lanfranco