Creating a base test

Hi All,

I am new to the UVM. I am currently working in USB Project. I have written one testcase (test.svh), which performs basic usb_enumeration. This test.svh contains all the things (build phase, run_phase, etc…). Now, I need to write 2nd testcase (test2.svh) to initiate data transfer in USB. But, in order to do that, enumeration should complete. I do not want to copy all the codes from test.svh and write one more function/task along with this for data transfer. I need to keep test.svh as a base test because it is required for all the testcases (test3, 4, 5 etc…).

Can any one suggest how can I keep this as a base test and write other testcase so that in the run phase of every testcase, I need to cover basic usb enumeration and additional tasks/functions according to the respective testcase.

It will be good if someone shares the example with regards to basic “Hello_wordl” uvm;

Lets say we have UVM environment to display “Hello_World” which consists (test.svh, env.svh and package file …).
Now, I need to write test2. svh in the same environment to display “Good Morning” and say “Good Afternoon” in test3. svh. But, while running test2.svh, I need to get first display “Hello_World” and then Good Morning, similarly for test3. svh also.

Please provide me some hints or link where this kind of example shown.

Thank you,

In reply to Mahesh K:

Though you can do this in UVM - I suggest you think about coding these as sequences than tests - as sequences are more easier to reuse. Coming to the specific code snippet - you would extend:


class test2 extends base_test;

  // override only main_phase
  // Leverage build/connect etc. from base_test

  // If you need base_test::run_phase use
  fork
    super.main_phase(phase);
  join_none


HTH
Srini
www.verifworks.com

In reply to Srini @ CVCblr.com:

Thank you, Srini.