Error-[SE] Syntax error
Following verilog source has syntax error :
Illegal identfier in binsof expression. Coverpoint identifier used
in this cross is expected.
“TESTBENCH/classes/env/atu_coverage.sv”,
91: token is ‘)’, column 94
bins wpmac = binsof (W_CID.LOW) && binsof (W_DID.LOW) ;
9 warnings
1 error
n what is the mistake here:-
W_PM_ACESS: cross addr_user_aw_cid , addr_user_aw_did {
bins wpmac = binsof (W_CID.LOW) && binsof (W_DID.LOW) ;
}
In reply to verificationengineer:
Most likely your cross needs to be written as
W_PM_ACESS: cross W_CID, W_DID {
bins wpmac = binsof (W_CID.LOW) && binsof (W_DID.LOW) ;
}
You need to cross the coverpoint labels to access the bins you have defined.
In reply to dave_59:
//============SAME error ====================//
Error-[SE] Syntax error
Following verilog source has syntax error :
Illegal bin identfier in binsof expression. Coverpoint or cross bin
identifier expected
“TESTBENCH/classes/env/atu_coverage.sv”,
95: token is ‘)’
bins wpmac = binsof (W_CID.low) && binsof
(W_DID.low) ;
^
9 warnings
1 error
//W_PM_ACESS: cross addr_user_aw_cid , addr_user_aw_did {
//
// bins wpmac=binsof(w_cid.low) && binsof(w_did.high) ;
// }
W_PM_ACESS: cross W_CID, W_DID {
bins wpmac = binsof (W_CID.low) && binsof (W_DID.low) ;
}
In reply to verificationengineer:
Could you please show your coverage code. I want to understand what is what when asking.
In reply to verificationengineer:
As I said above, You need to cross the coverpoint labels to access the bins you have defined.
The case of the labels must match. I had no way of knowing that they didn’t until you posted the full code.
W_PM_ACESS: cross w_cid, w_did {
bins wpmac = binsof (w_cid.low) && binsof (w_did.low) ;