Coverting verilog testcases to UVM

UVM
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1

Hi,

I am trying to port verilog testcases to UVM. Can you please give suggestions in how do I port it to UVM testbench.

Thanks,
Rajesh

2

In reply to tex_mex:

  1. Study SystemVerilog
  2. Study UVM
  3. Make a UVM testcase from scratch.

It’s going to be very hard for anyone here to help you without knowing more details about the design requirements or the existing Verilog testcases and testbench architecture. And what is the motivation behind this?