Coverting $setup and $hold violations into UVM_ERROR

Hi,

I am using memory model in verification, Which is using $setup and $hold for checking timing violation.
How to convert $setup/$hold into UVM_ERROR ?

Thanks
Saravanan

In reply to uvm_novice:

Timing checks have notifier variables that can be used to trigger a uvm_error. See Section 31.6 Notifiers: user-defined responses to timing violations in the IEEE 1800-2017 SystemVerilog LRM