I have a register model and defined covergroups and coverpoints inside it like below:
class REG0_type extends uvm_reg;
rand uvm_reg_field V;
virtual function void build();
V = uvm_reg_field::type_id::create(“V”);
V.configure(this, 1, 0, “RW”, 1, `UVM_REG_DATA_WIDTH’d0>>0, 1, 1, 1);
endfunction
covergroup wr_cg;
option.per_instance=1;
V : coverpoint V.value[0:0] {option.auto_bin_max = 2;}
endgroup
covergroup rd_cg;
option.per_instance=1;
V : coverpoint V.value[0:0] {option.auto_bin_max = 2;}
endgroup
protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);
super.sample(data, byte_en, is_read, map);
if(!is_read) wr_cg.sample();
if(is_read) rd_cg.sample();
endfunction
endclass
The filed V in DUT is volatle,will change from 0 to 1 by hardware automatically if certain conditions be met.
Some tests will create some scenario which will make V asserted in DUT and then read REG0 to get value of V.
The issue is with such tests, bins=[1] for rd_cg can never be hit.
I debuged and found i can observe an asserted V inside bus2reg of adapter inside register predictor. so I don’t understand why rd_cg can not sample an asserted V since test will read a REG0 and the V is asserted.