class atu_coverage extends uvm_component;
`uvm_component_utils(atu_coverage)
d_ip_atu_syn_ral_block regmodel ;
//virtual ips_if vif;
//d_ip_atu_syn_ral_block regmodel;
bit axi_clk;
bit ipg_clk;
d_ip_atu_cfg cfg;
bit [2:0] cid_arr ;
bit [4:0] did_arr;
bit EN;
bit [7:0] EVSEL;
bit [15:0] local_min_addr;
bit[15:0] local_max_addr ;
bit[15:0] sys_min_addr;
bit[15:0] sys_max_addr ;
//===============================================================
//=================Functional coverage ======================//
covergroup Clock_Connectivity ();
option.per_instance=1;
IPG_CLK: coverpoint ipg_clk {
bins LOW = {100} ;
bins MEDIUM ={200} ;
bins HIGH = {300} ;
}
AXI_CLK : coverpoint axi_clk {
bins LOW = { 200, 300,400,500} ;
bins High = {600, 700, 800} ;
}
endgroup
covergroup configuration_coverage ();
option.per_instance=1;
CID : coverpoint cid_arr {
bins LOW = {0};
}
I_CID: coverpoint cid_arr {
ignore_bins HIGH = { 1,2,3,4,5,6,7};
}
DID : coverpoint did_arr {
bins LOW = {1};
}
I_DID: coverpoint did_arr {
ignore_bins HIGH = {0 , [2:31]};
}
// cohort manager {cid ==1 to 7 , did ==1}
// other master (if did != 1)
CID_x_DID : cross CID , DID ;
ICID_x_IDID : cross I_CID , I_DID;
endgroup
covergroup atu_enb_dsb_coverage();
option.per_instance=1;
ENB_DSB: coverpoint EN { //regmodel.ATU.MSR0.
bins HIGH = {1} ;
bins LOW = {0};
}
endgroup
covergroup address_trans_cover();
option.per_instance =1;
EVSEL: coverpoint EVSEL { //regmodel.ATU.MCR.
bins BYPASS = {0};
bins MISS = {1};
bins HIT_DES_0 ={2};
bins HIT_DES_1 ={3};
bins HIT_DES_2 ={4};
bins HIT_DES_3 ={5};
bins HIT_DES_4 ={6};
bins HIT_DES_5 ={7};
bins HIT_DES_6 ={8};
bins HIT_DES_7 ={9};
bins HIT_DES_8 ={10};
bins HIT_DES_9 ={11};
bins HIT_DES_10 ={12};
bins HIT_DES_11 = {13};
bins HIT_DES_12 = {14};
bins HIT_DES_13 ={15};
bins HIT_DES_14 ={16};
bins HIT_DES_15 ={17};
bins HIT_DES_16 ={18};
bins HIT_DES_17 ={19};
bins HIT_DES_18 ={20};
bins HIT_DES_19 ={21};
bins HIT_DES_20 ={22};
bins HIT_DES_21 ={23};
bins HIT_DES_22 ={24};
bins HIT_DES_23 ={25};
bins HIT_DES_24 = {26};
bins HIT_DES_25 = {27};
bins HIT_DES_26 ={28};
bins HIT_DES_27 ={29};
bins HIT_DES_28 ={30};
bins HIT_DES_29 ={31};
bins HIT_DES_30 ={32};
bins HIT_DES_31 ={33};
bins HIT_DES_32 ={34};
bins HIT_DES_33 ={35};
bins HIT_DES_34 ={36};
bins HIT_DES_35 ={37};
bins HIT_DES_36 ={38};
bins HIT_DES_37 ={39};
bins HIT_DES_38 = {40};
bins HIT_DES_39 = {41};
bins HIT_DES_40 ={42};
bins HIT_DES_41 ={43};
bins HIT_DES_42 ={44};
bins HIT_DES_43 ={45};
bins HIT_DES_44 ={46};
bins HIT_DES_45 ={47};
bins HIT_DES_46 ={48};
bins HIT_DES_47 ={49};
bins HIT_DES_48 ={50};
bins HIT_DES_49 ={51};
bins HIT_DES_50 ={52};
bins HIT_DES_51 ={53};
bins HIT_DES_52 ={54};
bins HIT_DES_53 ={55};
bins HIT_DES_54 ={56};
bins HIT_DES_55 ={57};
bins HIT_DES_56 ={58};
bins HIT_DES_57 ={59};
bins HIT_DES_58 ={60};
bins HIT_DES_59 ={61};
bins HIT_DES_60 ={62};
bins HIT_DES_61 ={63};
bins HIT_DES_62 ={64};
bins HIT_DES_63 ={65};
bins HIT_DES_64 ={66};
}
LOCAL_MIN_ADDR : coverpoint local_min_addr { // IF_AW=49 bit parameterized == cfg.local_min_addr
bins LOW = {[0:64]} ;
bins MEDIUM = {[65:128]};
bins HIGH = {[129:$]};
}
LOCAL_MAX_ADDR : coverpoint local_max_addr { // IF_AW=49 bit parameterized == cfg.local_max_addr
bins LOW = {[0:64]} ;
bins MEDIUM = {[65:128]};
bins HIGH = {[129:$]};
}
SYS_MIN_ADDR: coverpoint sys_min_addr { // cfg.sys_min_addr
bins LOW = {[0:64]} ;
bins MEDIUM = {[65:128]};
bins HIGH = {[129:$]};
}
SYS_MAX_ADDR: coverpoint sys_max_addr { // cfg.sys_max_addr
bins LOW = {[0:64]} ;
bins MEDIUM = {[65:128]};
bins HIGH = {[129:$]};
}
endgroup
//==================================================================
function new(string name="", uvm_component parent);
super.new(name, parent);
Clock_Connectivity=new();
configuration_coverage=new();
atu_enb_dsb_coverage=new();
address_trans_cover=new();
endfunction
//=================== write function ====================================//
function void write_fun();
// t1= uart_transaction::type_id::create("t1");
$display("====================VERIFICATIONENGINEER==================================================", $time);
Clock_Connectivity.sample();
configuration_coverage.sample();
atu_enb_dsb_coverage.sample();
address_trans_cover.sample();
endfunction
endclass
///===================================
hii guys let me know why these covergroups not sampling , i am not expecting hit of bins just it should genetrate html report , report not generating why because covergroup not sampling , let me know please what is the error .