Coverage for Register Assistant Blocks

UVM
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1

I have been having all sorts of fun with the register package created from Register Assistant.

At the moment i am looking to analyze my coverage from a number of preliminary tests. However i am having trouble sampling any coverage.

Within my testbench i have instantiated the register model with the following code:


    // Create register model
    regmodel = registers_pkg::TOP_BLOCK::type_id::create("regmodel", this);
    reg2ocp = reg2ocp_adapter::type_id::create("reg2ocp", this);
    
	// Enable register model coverage
	uvm_reg::include_coverage("*",UVM_CVR_ALL);
    
    regmodel.build();
    `uvm_info("BLOCK_A_TB", {$sformatf("Created: %0s",regmodel.get_full_name())} , UVM_MEDIUM)

I have followed the advice from the cookbook and specified “include_coverage()”.

However when i look at all of the covergroups in questa there is nothing in any of the bins for the registers, as if my sample() is not being triggered.

Can anyone advise what i am doing wrong?

2

I have managed to solve my own problem here…

  1. you need a predictor either explicit as per mentors examples or via the built-in predictor

  2. you need to include coverage for all - this enables the block coverage!


// Enable register model coverage
	uvm_reg::include_coverage("*",UVM_CVR_ALL);
	
    // Create register model
    regmodel = registers_pkg::CTRL_TOP_BLOCK::type_id::create("regmodel", this);   
    regmodel.build();	    
    `uvm_info("BASE TEST", {$sformatf("Created: %0s",regmodel.get_full_name())} , UVM_MEDIUM)	
    
    reg2ocp = reg2ocp_adapter::type_id::create("reg2ocp", this);   
    `uvm_info("BLOCK_A_TB", {$sformatf("Created: %0s",reg2ocp.get_full_name())} , UVM_MEDIUM)
    
    // Build the register model predictor
    bus_agent2reg_predictor = uvm_reg_predictor #(OCP_transfer)::type_id::create("bus_agent2reg_predictor", this);
    // or enable built in predictor
    regmodel.default_map.set_auto_predict(1);

3 ) For the final trick of seeing the coverage for fields in each register you need to set coverage for the register model:


	tb.regmodel.set_coverage(UVM_CVR_FIELD_VALS);

However what you also need to do is sample these register manually with each access


        tb.regmodel.sample_values();

What follows on from this is auto bins for each register and with 32-bit registers this is a massive amount of coverage space. Does anyone know how to configure these?

Any thoughts are always welcome, thanks