Coverage problem using makefile

Hello people,

I have modified and adapted the makefile example provided here for interacting with Matlab.
Everything works except the coverage. I do not know why questa is not taking the “coverage” parameter
with the vsim command.

The Makefile is:

Makefile for MATLAB integration example

Note: QUESTA_SIM needs to be set to the Questa Installation Path

MATLAB needs to be set to MATLAB Installation Path

This is configured for 64bit mode. Change as needed for 32bit mode

VLOG_ARGS :=
VSIM_ARGS = -voptargs=+acc
MODULATION :=

all: simulate_sv simulate_matlab config_file simulate_matlab_BPSK simulate_matlab_QPSK simulate_matlab_8PSK

clean:
rm -rf work/ transcript *.wlf *.so *.o *.log *.ucdb *~ *#

compile_sv_tb:
#First I compile the VHDL:
vcom -mixedsvvh DUT/package_SEC/sec_common.vhd
vcom +cover -f dut.f
#Then I compile the SV files
vlog {VLOG_ARGS} {MODULATION} -f tb.f

create_work:
vlib work

optimize:

compile_qmw:
vlog qmw/qmw_sv/questa/qmw_hdl2matlab.sv
vlog qmw/qmw_sv/questa/qmw_post_sim.sv
$(eval VLOG_ARGS := +define+QMW)

simulate_matlab_BPSK: clean create_work define_BPSK simulate_matlab

simulate_matlab_QPSK: clean create_work define_QPSK simulate_matlab

simulate_matlab_8PSK: clean create_work define_8PSK simulate_matlab

define_BPSK:
(eval MODULATION := +define+BPSK) define_QPSK: (eval MODULATION := +define+QPSK)
define_8PSK:
$(eval MODULATION := +define+EIGHTPSK)

simulate_matlab: compile_qmw compile_sv_tb
@echo “Simulating with MATLAB Scoreboard using qmw”
/usr/local/MATLAB/R2016a/bin/matlab -nosplash -r ‘run MATLAB/start.m’ &
sleep 10
vsim -64 -coverage +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_64 top -c -do “qmw_demo.do”

post_sim_sb_qmw:
matlab -nosplash -r ‘run MATLAB/start.m’ &
sleep 10
vsim -voptargs=“+acc” qmw_post_sim -sv_lib qmw/qmw_sv/questa/qmw_client_64 -do “qmw_post_sim.do”

.PHONY: all clean

And the “qmw_demo.do” file is:


source qmw/qmw_sv/questa/qmw_hdl2matlab.tcl

add wave top/DUT/*

run -all

Coverage
coverage attribute -name TESTNAME -value random_test_matlab
coverage save random_test_matlab.ucdb
coverage report -code s -details -file code_coverage.txt
vcover report random_test.ucdb -cvg -details
vcover report -html random_test_matlab.ucdb
coverage report -code sbefc -details -file coverage.txt

quit

I would really appreciate your help.
Thanks in advance,
Antonio

P.S. I have posted it as plain text because the forum (as far as I know) only permits pasting VHDL/VERILOG/SV code.

In reply to antonio92m:

You have to compile and simulate for coverage:
vlog +cover +incdir+$env(UVM_HOME)/src +incdir+…
vsim -onfinish stop -wlfnocollapse -sv_lib $env(UVM_DPI_LIB)/uvm_dpi -voptargs=+acc -assertdebug -displaymsgmode both -coverage -quiet …

Christoph

In reply to chr_sue:

Hello Chris,

Thank you for your reply.
I have done what you said, I compiled both VHDL and SystemVerilog with the “+cover” option.
Also added to the vsim command the arguents you mentioned:
vsim -64 -wlfnocollapse +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_64 -voptargs=+acc -assertdebug -displaymsgmode both -coverage -quiet top -c -do “qmw_demo.do”
But still it does not generate neither “.ucdb” file, nor the “.txt” or the html report.

Thank you,
Antonio

In reply to antonio92m:

I got it working transforming the makefile into a “.do” file.

Antonio