Hi,
I have a scenario where my sequence A is extending from sequence B.
There is a bit variable C in sequence B (default value 1’b1) which I am accessing in sequence A.
I am running sequence A in my test environment using command line arguments.
Is there any way where I can control the value of Variable C from the command line arguments only?
Thanks.
In reply to nitishg:
AFAIK, it cannot be controlled directly from the command line. But try using “$value$plusargs ()” and get it in the TB top from the command line argument and use config_db to set and get it in different places (like the test, sequences etc.) and see if it works.
In reply to nitishg:
With UVM 1.2, try using the command line option +uvm_set_config_int=comp,field,value in conjunction with uvm_config_db#(uvm_bitstream_t)::get( cntxt, inst_name, field_name, value )
package pkg;
`include "uvm_macros.svh"
import uvm_pkg::*;
class B extends uvm_sequence;
bit C = 1'b1;
`uvm_object_utils(B)
function new(string name="B");
super.new(name);
endfunction
virtual task pre_start();
void'(uvm_config_db#(uvm_bitstream_t)::get(null,get_full_name(),"C",C) );
endtask
virtual task body();
`uvm_info( "TRACE", $sformatf( "C=%b", C ), UVM_LOW )
endtask
endclass
class test extends uvm_test;
uvm_sequencer#(uvm_sequence_item) sqr;
`uvm_component_utils(test)
function new( string name="test", uvm_component parent=null );
super.new( name, parent );
endfunction
virtual function void build_phase( uvm_phase phase );
sqr = new("sqr", this); // cheat, factory not setup for this example type
endfunction
virtual task run_phase( uvm_phase phase );
B b;
b = B::type_id::create( "b", this );
b.start( sqr );
endtask
endclass
endpackage
module top;
import pkg::*;
import uvm_pkg::*;
initial run_test("test");
endmodule