Controlling the random seed for a verification env with UVM

UVM
,
1

I have these questions.

1] how to establish a random seed for a verification env with UVM?

2] what is the difference between using the $srandom(x) system function and passing the seed directly to $random(seed) or $urandom(seed)?

3] how is the seed applied in case using the method randomize()?

2

In reply to samerh:

  1. The seed for SystemVerilog simulation can be set by the command line of your tool. Please check the User Manual.
  2. $random is from Verilog and you should no longer be using it.
  3. $urandom and randomize are both controlled by the same SystemVerilog seeding mechanism. A good pair on this subject can be found here.