Control a UVM test by a scripting language (python)

Hello

I would like to know if it is possible to control an UVM testbench via a scripting language like python.
The design I have to verify will be controlled with Control/Status registers and those registers will be controlled with a python script.

Right now I am connecting my UVM environnement to systemC modules and the systemC run a python script that interact with the systemC modules.
I would like to know if there is a standard solution for this problem.

Thanks

Pierre-Antoine

It’s possible to control a UVM testbench from anything that has a C interface using SystemVerilog’s DPI. Actually, if you can open up an IPC socket from anything, you can write a C interface that connects to the socket and connect that the SystemVerilog through the DPI. If you can get away without using IPC sockets that would be the most efficient way to do it.

You may want to see these links

https://verificationacademy.com/seminars/uvm-recipe-c-based-stimulus-for-uvm

And read the paper “Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI”
https://verificationacademy.com/news/featured-technical-papers-dvcon-2013

Thanks for your answer I will look at that.

Hello ,
kindly find an example

Regards
Yassine

In reply to ylahlou:

Another example if you are interested
https://verificationacademy.com/forums/ovm/cosimulate-systemverilog-and-python#answer-63425

All the replies above are very clever. They all provided good solutions. If you want to make this UVM environment reusable for long term, you may consider to adopt COCOTB. It directly talks to your HDL from Python, but the underline infrastructure is similar to the solutions they provided above. You then can use the similar method provided by Jonathan Alvarez to pass strings to UVM TB, and use the UVM factory to create the sequence based on the string and to start the sequence on a sequencer. You can definitely reuse the VIPs/UVM sequences from both language domains. The randomization can also be done in UVM TB and passes back to COCOTB, since the simulator does good jobs on the constraint solving. We actually used this method to build the UVM-SV/COCOTB hybrid sim environment.

Our entire DV framework and test flow is Python driven. Believe it or not, we actually see much better sim performance improvement in pure COCOTB sims over the pure SVTB or UVM testbenches. This also depends on the types design or applications. In our case, the bus interface protocol is pretty simple, but The internal RTL logic is very heavy. The DV work requires a lot of complicated data processing to generate packets then to drive over the bus in binary format. That is why it runs fast. Python is shining in this domain. It works well in the native Python sim environment.

Another solution is to use the uvm-python package which is built on top of COCOTB. Refer to this link: uvm-python — uvm_python 0.3.0 documentation. This route is to make your entire test framework pretty much UVM alike.

I wish I can provide you some concrete examples to demonstrate the idea, but our design and verification code are under monitored within a confidential controlled environment. I can’t even copy and paste more than a few hundreds of letters outside of the environment. Unfortunately those examples are more than a few hundred words. If I upload a presentation slide or document, I will risk my career and could get fired.

Good luck!

Richard