In reply to cgales:
Here Cgales,
This is the functional coverage subscriber fc_subs.sv and next file is driver .sv:
/********************************************************************************/
Functional Coverage Subscriber
/********************************************************************************/
class fc_subs extends uvm_subscriber#(trans);
`uvm_component_utils(fc_subs)
trans tx;
covergroup cg;
one: coverpoint tx.in;
two: coverpoint tx.id;
three:coverpoint tx.reset;
cross one,two,three;
endgroup:cg
function new(string name,uvm_component parent);
super.new(name,parent);
cg = new;
endfunction
function void write(trans t);
tx = t;
cg.sample();
endfunction
endclass/********************************************************************************/
Driver File
/********************************************************************************/
class driver extends uvm_driver#(trans);
`uvm_component_utils(driver)
virtual intf drv_if;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
assert(uvm_config_db#(virtual intf)::get(this,"", "intf",drv_if));
endfunction
task run_phase(uvm_phase phase);
trans trx;
forever begin
@drv_if.mtr;
seq_item_port.get_next_item(trx);
@drv_if.mtr;
drv_if.mtr.in <= trx.in;
drv_if.mtr.id <= trx.id;
seq_item_port.item_done();
end
endtask
endclass/**************************************************************************/
Transaction File
/**************************************************************************/
class trans extends uvm_sequence_item;
rand bit[7:0]in;
rand bit[1:0]id;
bit[15:0]out;
bit reset;
constraint c2 {id inside {[0:3]};}
function new(string name = "trans");
super.new(name);
endfunction
`uvm_object_utils_begin(trans)
`uvm_field_int(in,UVM_ALL_ON)
`uvm_field_int(id,UVM_ALL_ON)
`uvm_field_int(out,UVM_ALL_ON)
`uvm_field_int(reset,UVM_NONE)
`uvm_object_utils_end
endclass/*********************************************************************************/
Interface File
/*********************************************************************************/
interface intf(input bit clk, input bit reset);
logic [1:0] id;
logic [7:0] in;
logic [15:0]out;
clocking mtr@(posedge clk);
default input #1step output #1step;
input out;
output id,in;
endclocking
clocking slv@(posedge clk);
default input #1step output #1step;
output out;
input in,id;
endclocking
modport mtr_mp(input clk,reset,out, output id,in);
modport slv_mp(input clk,reset,in,id, output out);
modport mtr_mp_syn(clocking mtr);
modport slv_mp_syn(clocking slv);
endinterface
/***************//*****************//******************************//******************
/**************************************************************************************
Please guide.
Thanks and Regards
Sunil S.
