Constructor of functional coverage subscriber

Hello Forum,

I am writing the functional coverage subscriber and while writing the constructor as given below, i am facing an issue.
The class is given below:

class fc_subs extends uvm_subscriber#(trans);
  `uvm_component_utils(fc_subs)
  
  trans tx;
  covergroup cg;
  one: coverpoint tx.in;
  two: coverpoint tx.id;
  three:coverpoint tx.reset;
  
  cross one,two,three;
endgroup:cg

  function new(string name = "fc_subs", uvm_component parent = null);
  super.new(name,parent);
  cg = new;
  endfunction:new 
  
  function void write(trans t);
    tx = t;
    cg.sample();
  endfunction  
  
endclass

It is giving error in new function in super.new line:

# ** Error: (vsim-8754) C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_registry.svh(66): Actual input arg. of type 'class mtiUvm.uvm_pkg::uvm_component' for formal 'name' of 'new' is not compatible with the formal's type 'string'.
# 
#         Region: /uvm_pkg::uvm_component_registry #(pkg::fc_subs, fc_subs)
# ** Error: (vsim-3046) C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_registry.svh(66): Too many arguments to 'new'. Expected 1, found 2.

Please help and suggest some workaround.

Thanks and Regards
Sunil S.

In reply to sunils:

Your code compiles correctly for me. Are you sure that this is where the errors are pointing to?

Since the errors are pointing to the uvm_registry.svh code with too many arguments, I’m going to guess that you have an issue where you are using uvm_component_utils where you should be using uvm_object_utils. Check your sequence items.

In reply to cgales:

Hello Cgales,

Alongwith the above error, i am also getting the following error:, which i am actually concerned in the previous as above:

Region: /uvm_pkg::uvm_component_registry #(pkg::fc_subs, fc_subs)
# ** Error: (vsim-8268) driver.sv(19): No Default value for formal 't' in task/function get_next_item.
# 
#         Region: /pkg::driver
# ** Error: (vsim-8268) fc_subs.sv(14): No Default value for formal 'parent' in task/function new.

I am using the uvm_object_utils only in sequence and transaction class. And in the rest of the environment alongwith subscriber i am using the uvm_component_utils.
Please suggest some solution for the above error in fc_subs.sv and driver.sv file

Thanks and Regards
Sunil S.

In reply to sunils:

I can’t respond without seeing the code in question.

You need to post the code that is generating the errors, preferably a complete example that can be compiled and shows the error.

In reply to cgales:

Here Cgales,

This is the functional coverage subscriber fc_subs.sv and next file is driver .sv:

//
Functional Coverage Subscriber
/
/

class fc_subs extends uvm_subscriber#(trans);
  `uvm_component_utils(fc_subs)
  
  trans tx;
  covergroup cg;
  one: coverpoint tx.in;
  two: coverpoint tx.id;
  three:coverpoint tx.reset;
  
  cross one,two,three;
endgroup:cg

  function new(string name,uvm_component parent);
  super.new(name,parent);
  cg = new;
  endfunction
  
  function void write(trans t);
    tx = t;
    cg.sample();
  endfunction  
  
endclass

//
Driver File
/
/

class driver extends uvm_driver#(trans);
  `uvm_component_utils(driver)
  
  virtual intf drv_if;
  
  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    assert(uvm_config_db#(virtual intf)::get(this,"", "intf",drv_if));
  endfunction
  
  task run_phase(uvm_phase phase);
    trans trx;
  forever begin
    @drv_if.mtr;
  seq_item_port.get_next_item(trx);
    @drv_if.mtr;
    drv_if.mtr.in <= trx.in;
    drv_if.mtr.id <= trx.id;
  seq_item_port.item_done(); 
   end
  endtask  
endclass

//
Transaction File
/
/

class trans extends uvm_sequence_item;
  rand bit[7:0]in;
  rand bit[1:0]id;
       bit[15:0]out;
       bit reset;
  
  constraint c2 {id inside {[0:3]};}
  
  function new(string name = "trans");
    super.new(name);
  endfunction
  
  `uvm_object_utils_begin(trans)
    `uvm_field_int(in,UVM_ALL_ON)
    `uvm_field_int(id,UVM_ALL_ON)
    `uvm_field_int(out,UVM_ALL_ON)
    `uvm_field_int(reset,UVM_NONE)
  `uvm_object_utils_end
  
endclass

//
Interface File
/
/

interface intf(input bit clk, input bit reset);

logic [1:0] id;
logic [7:0] in;
logic [15:0]out;

clocking mtr@(posedge clk);
  default input #1step output #1step;
  input out;
  output id,in;
endclocking

clocking slv@(posedge clk);
  default input #1step output #1step;
  output out;
  input in,id;
endclocking

modport mtr_mp(input clk,reset,out, output id,in);
modport slv_mp(input clk,reset,in,id, output out);
modport mtr_mp_syn(clocking mtr);
modport slv_mp_syn(clocking slv);

endinterface

///////
/
****************************************************************************

Please guide.

Thanks and Regards
Sunil S.

In reply to sunils:

//
Test File
/
/

class test extends uvm_test;
  `uvm_component_utils(test)
  
  environ env;
  
  function new(string name = "test", uvm_component parent);
    super.new(name,parent);
  endfunction  
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = environ::type_id::create("env",this);
  endfunction
  
  task run_phase(uvm_phase phase);
    my_seq seq;
    phase.raise_objection(this);
    
   seq = my_seq::type_id::create("seq");
  assert(seq.randomize());
  `uvm_info("Merge Test",{"\n", seq.sprint() }, UVM_LOW)
  seq.start(env.jb_agent.seqr);
  #50ns;
  phase.drop_objection(this);
  
  endtask  
endclass

/**********************************************************************************
                      Environ
/**********************************************************************************
class environ extends uvm_env;
  `uvm_component_utils(environ)
  
  agent         jb_agent;
  fc_subs       jb_fc_sub;
  scoreboard    jb_sb;
 
  
  function new(string name = "environ", uvm_component parent);
    super.new(name,parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      jb_agent  = agent::type_id::create("jb_agent", this);
      jb_fc_sub = fc_subs::type_id::create("jb_fc_sub",this);
      jb_sb     = scoreboard::type_id::create("jb_sb", this);
    endfunction: build_phase
 
   function void connect_phase(uvm_phase phase);
      super.connect_phase(phase);
      jb_agent.agt_ap.connect(jb_fc_sub.analysis_export);
      jb_agent.agt_ap.connect(jb_sb.sbd_ae);
   endfunction: connect_phase
endclass

In reply to sunils:

There is still missing code, but you can check the following:

For the new function, you should specify default values for the name and parent:


class driver extends uvm_driver#(trans);
  `uvm_component_utils(driver)
 
  virtual intf drv_if;
 
  function new(string name="driver", uvm_component parent=null);
    super.new(name,parent);
  endfunction

Also, make sure that the sequencer is typed to match the driver.