Folks;
When is the constructor “function new” called with reference to the build phase? Does the construction go before or after the build phase? Why?
Pls help!
In reply to samerh:
There is no UVM “construction phase”. But it’s inside the UVM build_phase functions that we call the SystemVerilog class constructors.
In reply to dave_59:
at which stage the constructors are called inside the buid_phase? at begging … middle or end?
UVM uses the phasing mechanism so that the test bench is properly constructed and synchronised. Build_phase() method is one of those phases, in which the verification components like driver, sequencer and other components are constructed at the same time.
To construct an object using factory, one needs to call component_handle_name = component_type::type_id::create(“component_handle_name”,this);.
After constructing the required components in build_phase(), the connect_phase() method is used to connect all the components.
In reply to samerh:
build_phase executes from top to bottom. which means the top most component is constructed first and then underlying components are created based on the configuration parameters.