Constraints

UVM
1

Hi,

I am trying to verify dual-ported RAM and to check for functional correctness I decided to implement consecutive write and then reads on the same memory location to check whether it captures the latest transaction updated.

How can I constraint my testbench data variables in order to verify the desired functionality and check for the same in the checker? What should be my inline constraint?

2

In reply to sai_pra99:

That’s the address. You want to write and directly after read from the same location. But this is a stupid scenario. Better is to write to several loactions and then read in a diiferent order from the same locations.