Constraint the variable

Is there any method in sv or uvm to constraint the value of the variable without using constraint method ?

In reply to Vipulkumar:

You can use $urandom_range().

int sig1;

sig1 = $urandom_range(5,12);
constraints the value if sig 1 in the range 5 to 12.

$urandom_range(hi,lo) is the easiest to use.
If you want to use any constraint, try:

success = std::randomize( a, b, c ) with { a < b ; a + b < length ; };

You can get a free copy of the SystemVerilog LRM with lots of these ideas from the IEEE
I use mine every day!