Hi
I have a problem in constraint in sequence
my constraint is
(1) If TXC is all zeroes:
64 bit TXD should be a multiple of 3 and 4, and TXD cannot contain
64’h06_06_06_06_06_06_06_06 or 64’h07_07_07_07_07_07_07_07
(2) If any bit of TXC[7:0] is 1, possible values of TXD are :
64’h06_06_06_06_06_06_06_06 or 64’h07_07_07_07_07_07_07_07
(3)The number of blocks sent from sequence should be even
txc and txd is input
my sequence class
class base_seq extends uvm_sequence#(seq_item);
seq_item tx;
`uvm_object_utils(base_seq)
function new(string name=“base_seq”);
super.new(name);
endfunction
task body();
repeat(60) begin
tx=seq_item::type_id::create(“tx”);
start_item(tx);
assert(tx.randomize() with {(txc==8'h00)->(txd%3==0)||(txd%4==0)&&(txd!=64'h06_06_06_06_06_06_06_06 || 64'h07_07_07_07_07_07_07_07);
(txc== 8'hff|| 8'h01||8'hf1||8'hfe|| 8'hfc|| 8'hf8|| 8'he0||8'hc0|| 8'h80)->(txd==64'h06_06_06_06_06_06_06_06 || 64'h07_07_07_07_07_07_07_07 );});
finish_item(tx);
end
endtask
endclass
I have done this but its not working and how to put 3rd condition in constraint