Constraint priority

UVM
, ,
1 
rand bit high_speed_sdr0_ddr1 ; 
rand bit [15:0] block_length;
rand bit hs200_en; 
rand bit [1:0] max_block_length ;  //  0=512; 1=1k ; 2=2k ; 3=reserved 4k;



constraint c_mac_blk_limit { 
   solve high_speed_sdr0_ddr1 before max_block_length;
   if (high_speed_sdr0_ddr1 == 1 && hs200_en == 0 )
   {
   (max_block_length == 0);
   }
   else
   {
    max_block_length inside {0,1,2};    //as the 3rd value (11) is reserved .
   }
}  

constraint c_block_length { block_length < =max_block_length  }

now here my question is that i want to prioritzie the upper write constraint first and c_block_length constraitn later …

so is is possible to give priority that way or i just have to mange up the logic in other way. ???

2

In reply to milin parekh:

You need to explain what you mean by priority. All active constraints must be satisfied. there are no levels of satisfaction—it’s true or false.

SystemVerilog does use the term priority when it comes to overriding or disabling active constraints, but I’m not sure that’s what you were thinking.

The solve before construct has no affect on the constraints, only the probability of values chosen from the solution set. See this post for a better explanation.

It might help to explain why the constraints you wrote here do not produce the results you are expecting