Constraint override

UVM
,
1

Hi,

I’m trying to override constraints from parents class.

Especially simplewrite.length {[1:5]} from {[1:255]}.

so i override constraint as the below.
but it does not work.
What am I supposed to do to resolve this problem?

For example)
In the myuservirtualsequencelib.sv

class my_vseq_c extends myubmvirtualsequence;
...
mastersimplewrite simplewrite;
...

constraint read_c {
simplewrite.length inside {[1:5]};
simplewrite.datavaliddelay {[0:10]};
}

virtual task body();
...
'uvm_do_on_with (simplewrite, p_sequencer, {
 simplewrite.addressspace == 'h00;
 simplewrite.address == 'h00;
})
...
endclass

In the myuvmseqlib.sv


class mastersimplewrite extends myubmsequence;
rand reg[31:0] datavailddelay;
rand reg[31:0] address;
rand int length;

constraint read_c {
 length inside{[1:255]};
 datavailddelay inside {[0:10]};
}
...
virtual task body();
...
'uvm_do_with...
...
endtask
endclass
2

In reply to UVM_LOVE:

Could you please refine/correct your code, especially class my_vseq_c myubmvirtualsequence;
What is mastersimplewrite?
My recoomedation for your code is to use parameters in the corresponding data members.

3

In reply to chr_sue:

In reply to UVM_LOVE:
Could you please refine/correct your code, especially class my_vseq_c myubmvirtualsequence;
What is mastersimplewrite?
My recoomedation for your code is to use parameters in the corresponding data members.

Hi, sue,
mastersimplewrite is sequence class.
and my_vseq_c is extended by myubmvirtualsequence class.

My point of question is that I’d like to override read_c constraint at my_vseq_c class.
But it does not work.

4

In reply to UVM_LOVE:

If you want to make the constraints more constricting, you can add them to the with constraint

virtual task body();
...
'uvm_do_on_with (simplewrite, p_sequencer, {
 addressspace == 'h00;
 address == 'h00;
 length inside {[1:5]};
})
...
endclass

Note there is no need to prefix all the variables with ‘simplewrite.’

But if you want to override with conflicting constraints, like length==256, you could either use soft constraints in the class mastersimplewrite, or you could use the factory to override the mastersimplewrite that provides an override for the constraint read_c.

5

In reply to dave_59:

In reply to UVM_LOVE:
If you want to make the constraints more constricting, you can add them to the with constraint

virtual task body();
...
'uvm_do_on_with (simplewrite, p_sequencer, {
addressspace == 'h00;
address == 'h00;
length inside {[1:5]};
})
...
endclass

Note there is no need to prefix all the variables with ‘simplewrite.’
But if you want to override with conflicting constraints, like length==256, you could either use soft constraints in the class mastersimplewrite, or you could use the factory to override the mastersimplewrite that provides an override for the constraint read_c.

Thanks Dave59. I have been done with first and second method from you. you are the best.
But you’ve introduced factory override method could not. so I’m trying to implement factory override as you said, could you guide for me how to implement factory override for override constraint with some snippet code?.