Constraint declaration

UVM
1

hi,
i am declaring in my transaction class below message:

rand bit[41:0] cpri_sts;
constraint CPRI_STS {wr_data [106:65] inside {[0:4398046511103]};}

it is 42 bit width declaration
but while running code it is showing warning your data width is more tha 2147483648

please help me how to declare above construct…

2

Your post doesn’t make a lot of sense.

First of all the constraint is for the top 42 bits of wr_data, not for cpri_sts.

Then the constraint for wr_data is meaningless, you’re asking for the value generated by randomization to be within the natural range of a 42 bit variable, so the constraint is vacuous.

What are you trying to do?

3

In reply to mperyer:

please follow the below code:

class fft_cmd_data_item extends fifo_controller_data_item #(`CMD_IN_WD);

bit [`CMD_IN_WD - 1:0] wr_data;
rand bit mode;
rand bit [2:0] cpri_lnk_no ;
rand bit [1:0] bypass_onebyn ;
rand bit [3:0] iqw_sel ;
rand bit [11:0] stage_sf ;
rand bit [3:0] output_sf ;
rand bit [3:0] cyclic_pi ;
rand bit [3:0] apri_axn_no ;
rand bit [17:0] cb_len ;
rand bit [7:0] q_num ;
rand bit [41:0] cpri_sts ;

constraint CPRI_STATUS {cpri_sts inside {[0:4398046511103]};}

simulation giving warning below statement:

Warning-[DCTL] Decimal constant too large
/trnitem/fft_data_item.sv, 280
Decimal constant is too large to be handled in compilation.
Absolute value 4398046511103 should be smaller than 2147483648

please help me how to set range for cpri status signal in the costraint declaration