I'm learning about UVM for verification. I got the test for verification planning & bug curve. The test is below:
The 1st question is : What is purpose (intention of designer) for flip flop insertion in this design ?
=> As my understanding, I think designer use flip flop to make the Data Stability to Avoid Data Loss. Do we have another intention for this modification ?
The 2nd question is : Do we have any failure operation(bug) case in such modification ?
=> I consider about timing bug. It means that the timing between PENABLE , PSEL input from master (without delay) & response from slave (with delay 1cycle).
PENABLE must still be generated by the APB master so that simpler APB peripheral designs can just detect the "setup" and "access" phases of each transfer by gating together PSEL, PENABLE and PREADY. The access phase might be wrong in this case.
=> Beside that, I cannot think another potential bug for this modification . If you have any idea, please share with me.
The 3rd question is : Could we change the modification method to keep intention of designer & avoid some bug as above ?
=> I do not have any idea for this question. Please share with me your thinking.
I'm so sorry about my English. You can feel so hard to understand what I described in above. Please share any question, thinking . I will try explain any your unclear point.