Connecting interface port with the module

UVM
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1

Hello, may this question looks basic for some of you ,I verified full adder using some additional inputs and outputs for controllability and observability and i have to verify ripple carry adder .since one of the aims of UVM is reusability i think I can use the module of full adder as it is ,in other words,i can use FA with those additional signals to build RCA .my question:
how to build rca using fa module connected with interface modports ? or I have to build a FA without those additional pins to build rca ?
//////////**** code of FA

module adder(input_if.port inter, output_if.port out_inter,  
  output  enum logic [1:0] {INITIAL,WAIT,SEND} state);
    
    always_ff @(posedge inter.clk)
        if(inter.rst) begin
            inter.ready <= 0;
            out_inter.data <= 'x;
	    out_inter.carry <= 'x;
            out_inter.valid <= 0;
            state <= INITIAL;
        end
        else case(state)
                INITIAL: begin
                    inter.ready <= 1;
                    state <= WAIT;
                end
                
                WAIT: begin
                    if(inter.valid) begin
                        inter.ready <= 0;
                        out_inter.data <= inter.A ^ inter.B ^ inter.Cin;
			out_inter.carry <= inter.A * inter.B +inter.A * inter.Cin + inter.Cin * inter.B;
                        out_inter.valid <= 1;
                        state <= SEND;
                    end
                end
                
                SEND: begin
                    if(out_inter.ready) begin
                        out_inter.valid <= 0;
                        inter.ready <= 1;
                        state <= WAIT;
                    end
                end
        endcase
endmodule: adder

/////***code of interface input

interface input_if(input clk, rst);
    logic  A, B,Cin;
    logic valid, ready;
    
    modport port(input clk, rst, A, B,Cin, valid, output ready);
endinterface

//////*****code of interface output

interface input_if(input clk, rst);
    logic  A, B,Cin;
    logic valid, ready;
    
    modport port(input clk, rst, A, B,Cin, valid, output ready);
endinterface
2

In reply to Imane EL:

You are declaring input_if twice (see your code).
What is the reason for working with input_if and output_if in your module port list.
It is common to have in your case only 1 interface covering all inputs and all outputs.