I am looking for a clean solution to connect interfaces (and thereby monitors) to internal modules of a DUT. My env looks close to this -
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An instance of DUT (dut_inst) has multiple sub-blocks within it. Let’s say we have one such block - blk_a
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Let us say blk_a has 3 ports - inputs port1 and port2; output port3
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There’s an equivalent interface file defined for blk_a -
interface blk_a_intf (input clk, input rst);
logic port1;
logic [1:0] port2;
logic [2:0] port3;
clocking drv @(posedge clk);
input port1;
input port2;
output port3;
endclocking
clocking mon @(posedge clk);
input port1;
input port2;
input port3;
endclocking
modport driver (clocking drv, input clk, rst);
modport monitor (clocking mon, input clk, rst);
endinterface
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The rtl does not use the above interface files. So these get used only in the verification environment to connect properly to the rtl signals.
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The modport ‘monitor’ gets used inside the monitor for getting the transaction data. I would like to hook this monitor to the internal block’s (blk_a) ports. Something like -
blk_a_intf.monitor.mon.port1 gets connected to dut.blk_a.port1
blk_a_intf.monitor.mon.port2 gets connected to dut.blk_a.port2
…
What’s the best way to do this?