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  • connecting the dut signals with interafce signals in the test bench top

connecting the dut signals with interafce signals in the test bench top

UVM 7030
lohithkumar.shivamurthy@tessolve.com
lohithkumar.shivamurthy@tessolve.com
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3 posts
September 21, 2023 at 10:00 pm

i have signal in the design A[1:0], how can i connect(instantiation) signals in the test bench top with signals test_data, i am having confusion like the design signal is if array A[1:0], how can we connect that ,i tried that .A[1:0](if.test_data[1:0]),
please suggest any idea for the same

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chr_sue
chr_sue
Full Access
4032 posts
September 22, 2023 at 6:41 am

In reply to lohithkumar.shivamurthy@tessolve.com:

You can connect to any internal DUT signal using the SV bind-construct.
Search the verification academy for more details.

lohithkumar.shivamurthy@tessolve.com
lohithkumar.shivamurthy@tessolve.com
Full Access
3 posts
September 26, 2023 at 1:05 am

i have to implement the one logic in the uvm driver,
we have one signals "tst" in the same signal we have to send do the both read and write, in the write method i have send the 32 bit addres , 4 addresses, each having 8 bit wide, once that is done need to send the data in the same signal of 32 bit data each having the 8 bit wide or byte, How can i implement the driver logic to send the
addr3 adrr2 addr1 addr0
1) 0001 0000 | 0000 0000 | 0000 0000 | 0000 0100 (0x10000004)
in this manner in the driver logic ,please provide some idea

dave_59
dave_59
Forum Moderator
11451 posts
September 26, 2023 at 10:17 am

In reply to lohithkumar.shivamurthy@tessolve.com:

See https://verificationacademy.com/forums/downloads/updated-example-code-dvcon-paper-missing-link-testbench-dut-connection

— Dave Rich, Verification Architect, Siemens EDA

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