Configuring a parameter in top module through script

UVM
1

Hi,

In the UVM environment, I want to configure a parameter in the top module through shell script. Please suggest how this can be implemented.

As in case of VHDL, vsim -g<parameter_name>= can be used to pass the value to the generic variables. Is there anything similar in SystemVerilog.

2

In reply to shankar_logic:
SystemVerilog parameters are analgous to VHDL parameters, but overriding them from the command line script is not part of either standard and is tool specific. Please check the user manual of the tool you are using as this form is not for tool specific support.

3

I didn’t find anything in the user manual regarding this.