- What are the steps to be followed for configuration randomization?
- How to write a sequence using configuration randomization??
- How to minimize the test cases using configuration randomization??
In reply to Vignesh_18:
Are these random 
interview questions? Where did you see the term “Configuration Randomization”?
In reply to dave_59:
In reply to Vignesh_18:
Are these random
I saw this in one blog and i wanted to implement this in my project
In reply to dave_59:
In reply to Vignesh_18:
Do you have a link to it?
Yes, I am having and I wanted to learn more about it!!
In reply to Vignesh_18:
Typically configuration objects are randomized in a test. After randomization you can pass this configu.ration object to the config_db. In uvm_components or uvm_objects you can retrieve these objects from the config_db.
The benfit of using config objects is you do not use fixed values for certain class variables. Using randomized configuration objects increases the verification quality.
In reply to chr_sue:
Could you give me more insights about it and the steps to be followed and how to implement it??
How to use configuration randomization in sequence file??
In reply to Vignesh_18:
A very simple approach looks like tis:
class my_seq_config extends uvm_object; // don't register with the factory
rand bit set_count;
rand int count;
function new (int count_arg = 0);
count = count_arg;
endfunction
endclass
class my_test extends uvm_test;
...
function void build_phase(uvm_phase phase);
...
my_seq_config cfg = new; // Constructing the config_object
if (!cfg.randomize() with { count < 16;})
uvm_config_db #(my_top_seq_config)::set(this, "*.*seq*", "config", cfg);
env = top::type_id::create("env", this);
endfunction
...
Then you can retrieve the randomized value in your sequence.
In reply to chr_sue:
In reply to Vignesh_18:
A very simple approach looks like tis:
class my_seq_config extends uvm_object; // don't register with the factory
rand bit set_count;
rand int count;
function new (int count_arg = 0);
count = count_arg;
endfunction
endclass
class my_test extends uvm_test;
...
function void build_phase(uvm_phase phase);
...
my_seq_config cfg = new; // Constructing the config_object
if (!cfg.randomize() with { count < 16;})
uvm_config_db #(my_top_seq_config)::set(this, "*.*seq*", "config", cfg);
env = top::type_id::create("env", this);
endfunction
...
Then you can retrieve the randomized value in your sequence.
Thanks a lot sir
Another doubt I am having here @chr_sue
- CAN’T WE CREATE THIS CONFIG CLASS AS A SEPEARTE CLASS LIKE ENV_CONFIG AND THEN WE CAN SET- GET??
- SHOULD WE CREATE THIS CONFIG AS SUB AGENT CONFIG CLASS AND DECLARE IT IN ENV_CONFIG??
WHICH ONE IS CORRECT??
In reply to Vignesh_18:
You can have config classes on each hierarchy level. There is no limitation.
You can have a top_config, env_config and several agent_ configs.
In reply to chr_sue:
In reply to Vignesh_18:
You can have config classes on each hierarchy level. There is no limitation.
You can have a top_config, env_config and several agent_ configs.
Thanks a lot Sir!!
Also, i tried implementing it and i got a following error
Error: (vsim-7073) …/wb_agt/uart_seqs.sv(143): Attempt to dereference null class reference (local::this.r_cfg.lcr) in constraint.
Time: 270 ns Iteration: 5 Process: /uvm_pkg::uvm_sequence_base::start/fork#294_f6a9bf8 File: …/wb_agt/uart_seqs.sv Line: 143
** Error: Assertion error.
Here is the code:
Sequence part
class base_seq extends uvm_sequence#(uart_xtn);
`uvm_object_utils(base_seq)
reg_config r_cfg;
function new(string name="base_seq");
super.new(name);
endfunction
endclass
//---------------------------------------------------------FULL DUPLEX----------------------------------------//
class seq1 extends base_seq;
`uvm_object_utils(seq1)
function new(string name="seq1");
super.new(name);
endfunction
virtual task body();
begin
req=uart_xtn::type_id::create("req");
if(uvm_config_db#(reg_config)::get(null,"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
//------------------------------------------LCR-->DLR REG ACCESS---------------//
start_item(req);
assert(req.randomize()with{wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
//-------------------------------------------DLR_MSB--------------------------//
start_item(req);
assert(req.randomize()with{wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
finish_item(req);
//-------------------------------------------DLR_LSB-------------------------//
start_item(req);
assert(req.randomize()with{wb_dat_i==8'b0011_0110;wb_we_i==1'b1;wb_addr_i==0;})
finish_item(req);
//-------------------------------------------LCR-->NORMAL REG ACCESS---------------//
start_item(req);
assert(req.randomize()with{wb_dat_i[7:2]==0;wb_dat_i[1:0]==r_cfg.lcr;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
reg_config class
class reg_config extends uvm_object;
`uvm_object_utils(reg_config)
rand bit [1:0] lcr;
function new(string name="reg_config");
super.new(name);
endfunction
endclassIn reply to Vignesh_18:
You don’t get the cfg object in your sequence and your check is wrong:
if(uvm_config_db#(reg_config)::get(null,"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
Please note the sequence does not belong to the hierarchy of the UVM testbench.
Please use
if(!uvm_config_db#(reg_config)::get(get_sequencer(),"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
In reply to Vignesh_18:
Your call to retrieve objects in the sequence is not correct
if(uvm_config_db#(reg_config)::get(m_sequencer,"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
or
if(uvm_config_db#(reg_config)::get(null,get_full_name(),"reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
In reply to chr_sue:
In reply to Vignesh_18:
You don’t get the cfg object in your sequence and your check is wrong:
if(uvm_config_db#(reg_config)::get(null,"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
Please note the sequence does not belong to the hierarchy of the UVM testbench.
Please use
if(!uvm_config_db#(reg_config)::get(get_sequencer(),"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
Thank you Sir!!
In reply to chr_sue:
In reply to Vignesh_18:
You don’t get the cfg object in your sequence and your check is wrong:
if(uvm_config_db#(reg_config)::get(null,"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
Please note the sequence does not belong to the hierarchy of the UVM testbench.
Please use
if(!uvm_config_db#(reg_config)::get(get_sequencer(),"","reg_config",r_cfg))
`uvm_fatal("R_CFG","Failed to get()")
After Doing subsequent changes into sequence file, I am getting fatal error…
UVM_FATAL …/wb_agt/uart_seqs.sv(33) @ 0: uvm_test_top.envh.agt_top.uart_agt[0].sqrh@@s1 [R_CFG] Failed to get()
In reply to Vignesh_18:
I do not see your set to the config_db.
Could you please put your code into an example of the edaplayground.com.
In reply to chr_sue:
In reply to Vignesh_18:
I do not see your set to the config_db.
Could you please put your code into an example of the edaplayground.com.
In the Test file i have pasted
function void uart_base_test::build_phase(uvm_phase phase);
env_config=uart_env_config::type_id::create("env_config");
r_cfg=reg_config::type_id::create("r_cfg");
if(has_wb_agent)
env_config.agt_config=new[no_of_duts];
config_uart;
uvm_config_db#(reg_config)::set(this,"*","reg_config",r_cfg);
uvm_config_db#(uart_env_config)::set(this,"*","uart_env_config",env_config);
super.build_phase(phase);
//ENVIRONMENT CREATION//
envh=uart_env::type_id::create("envh",this);