Hi All ,
I have the following scenario :
- An interface instantiated in a CSR module ( only for UVM Verification simulations ) sets a parameter via uvm_config_db via an initial block at Time 0 . The CSR module is an IP at a lower level in a SOC chip top DUT .
- The parameter is fetched ( via uvm_config_db :: get ) by a RAL file via reg_block's build() . The build() for the root block is called in Env's build_phase() .
Now the requirement is to override the parameter via top_tb via uvm_config_db :: set from an initial block ( different than the one which calls run_test ) .
Since both set are essentially done at Time 0 from a static entity ( prior to phasing ) , is there a precedence between the two settings ?
In the top_tb I tried setting it after using #0; delay and I observe it does override the parameter set from the interface .
Does the compilation order have an impact on the uvm_config_db :: set precedence ? As in latter compiled files would set it later giving a last write wins