1.)Why we are only getting the virtual interface using config_db in Build phase only ?
2.)Can we get in other sequential phases like end_of_eleaboration_phase, start_of simulation phase etc and if so then why ?
3.)Can we get it in other phases like in RUn Phase or during Run time and if so then why ?
In reply to aman007kr:
The config_db is a mechanism to send data through the UVM topology or to share data between other objects. It is not related to any phase. Sequences do not have the phases, but you can retrieve any data from the config_db.
BTW you should get the virtual interface in the connect_phase. Then you’ll be sure all components do exist.
In reply to chr_sue:
So are we just making sure that all the components will be available before the execution of all other phases after build_phase ?
In reply to aman007kr:
Sounds a little bit confusing to me, but at the end of build_phase all components of our UVM testbench will exist. Afterwards you can start to connect the components in the connect_phase.
In reply to aman007kr:
In reply to chr_sue:
So are we just making sure that all the components will be available before the execution of all other phases after build_phase ?
Yes. You are right. build_phase will create all the components that you intend your testbench env to have. Once this is done you can make the necessary connections in connect_phase between the built components.