Concept of UVC

Is there a concept of UVC in UVM? Is it same as UVM agent?

In reply to verif_learner:

If you mean the terminology Universal Verification Component (uVC) used in e, the more general term being used is Verification Intellectual Property (VIP) for a particular interface or protocol. That includes the UVM agent and its associated drivers, monitors, sequences, as well as the SystemVerilog interface that connects to your DUT.

In reply to dave_59:

Correct, I think UVC seems to have its genesis in Cadence.
But in UVC definition, they seem to show UVC encapsulating multiple agents + scoreboard + coverage etc. It looks like a more defined way of creating UVM ENV.

In reply to verif_learner:

The UVM gives you more freedom to define your concept of VIP, depending on your decisions.
The UVC, coming from Verisity and not from Cadence, is more restrictive.