Complex FPGA Design verification methodology

UVM
1

Dear members,

I have a complex FPGA design mostly built from schematic entry method( > 100 schematics) and a few VHDL files. I am new to verification topics and hence wanted to know what is the best method to verify the complete FPGA design. My questions are:

  1. Will writing only the testbench for the top level design help, or should I verify each and every schematic individually by writing testbench to each of them.
  2. Should I use System verilog for writing testbenches, or writing them in VHDL is fine? I have experience of writing testbenches only in VHDL.
  3. Kindly provide link to any resource or guides which could help me in this task.

Thank you very much in advance!

2

In reply to Echotwozero:

  1. At the very least you need top level (system) tests. If the smaller units (schematics) have specifications, or you can infer their specifications from the system specification, then you can test those as needed.

  2. In my opinion VHDL is fine for unit testing, but any verification environment of reasonable complexity should be written in SystemVerilog (or c++).

3

In reply to sbellock:

Thank you sbellock.

4

Just use board/FPGA testing~
Upload all code in the board and start playing with the board/FPGa.
When you see issues on the board/FPGA, than start analyse how you can develop test-bench for that functionality to debug.

And also do not forget to add ILA modules, as many as you can~