Compilation stops after parsing

Hi… I have included files at the top of ‘top’ module… All these files are getting parsed… But the compilation stops with syntax error just after parsing the last file (which is ‘test.sv’). I wanted to know whether this happens because of an error in the last file which is ‘test.sv’ or could it be because of an error in any of the other “included” files…?

In reply to slashdot:

I gone through such problem. Most of time its file which included before test.sv has some error it would come out from simulation.
Please confirm that.

In reply to Vinay Jain:

Hi Vinay… Thanks for the response… Would like a bit of better understanding about your answer. Will all the files still get parsed if there is an error of some sort in a file included before ‘test.sv’…?

In my testbench, all files including ‘test.sv’ are getting parsed. Compilation stops after that. I am not able to find any syntactical errors in ‘test.sv’ file. So am confused as to which file might be misbehaving.

In reply to slashdot:

Yes, I mean to say the file which is parsed just before test.sv file.
eg. file.list
incldue "driver.sv" include “test.sv”

So in this case please check syntax in driver.sv!

In reply to Vinay Jain:

Hi,

Can you please tell me what error you are getting ?

Regards
Chetan Shah

In reply to cashah85:

I am getting following error :


Parsing included file ‘env.sv’.
Back to file ‘package.sv’.
Parsing included file ‘test1.sv’.
Back to file ‘package.sv’.

Error-[SE] Syntax error
Following verilog source has syntax error :
“package.sv”, 30: token is ‘endpackage’
endpackage : pkg
^
System verilog keyword ‘endpackage’ is not expected to be used in this
context.

All my “included” files are inside ‘package.sv’. ‘test1.sv’ is the last file in ‘package.sv’.

In reply to slashdot:

Hi,

it would be great if you can share your complete package file. I just want to know what files are involved in compilation. I hope you have import your package in the top file.

Waiting for your reply.

Regards,
Chetan Shah

In reply to cashah85:

I bumped up with this problem earlier.

I am pretty sure some begin…end/endclass is missing in test1.sv file. can you please check.

Like Chetan mentioned,share your package file here.

In reply to Vinay Jain:

Thanks Vinay and Chetan for your suggestions and help.

I went through all the files in package. As Vinay suggested, I had missed out an ‘endclass’ in driver.sv. That was causing the problem.

Thanks again… :)…

In reply to slashdot:

I am glad I could help.