Compilation error cause by testbench package

All,

I have been attempting to compile my SPB testbench, but have came across a compilation error which I believe is caused by the testbench package which comprises of my `include macros. The package is shown below:

package spb_pkg;
    
    import uvm_pkg::*;
    `include "uvm_macros.svh"

    `include "spb_data_item.sv"
    `include "spb_agent_config.sv"
    `include "spb_env_config.sv"
    `include "spb_seq_lib.sv"
    `include "spb_sequencer.sv"
    `include "spb_driver.sv"
    `include "spb_monitor.sv"
    `include "reg2spb_adapter.sv"
    `include "spb_agent.sv"
    `include "spb_environment.sv"
    //`include "spb_coverage.sv"
    //`include "spb_scoreboard.sv"
    `include "spb_test_base.sv"


endpackage : spb_pkg

I use this package in my top level module as shown below:

`include "spb_if.sv"
`include "spb_pkg.sv"


//------------------------------------------------------------------------------------------------------
//Start Of Module
//------------------------------------------------------------------------------------------------------
module spb_top;

    //Import packages and include uvm macros
    import uvm_pkg::*;
    import spb_pkg::*;
    `include "uvm_macros.svh"

The error that I receive is regarding my spb environment component, so for completion the beginning of the environment code is shown below:

//------------------------------------------------------------------------------------------------------
//Start Of Class
//------------------------------------------------------------------------------------------------------
class spb_environment extends uvm_env;


    //------------------------------------------------------------------------------------------------------
    //Class Data Members
    //------------------------------------------------------------------------------------------------------
    spb_agent           spb_ag;                 //Handle to the SPB agent
    spb_env_config      spb_env_cfg;            //Handle to the environment configuration
    //spb_reg_coverage    spb_reg_fc_collector;   //Handle to SPB functional coverage subsciber
    //spb_scoreboard      spb_sb;                 //Handle to SPB scoreboard
    
    reg2spb_adapter     reg2spb;                            //Handle to the adapter
    uvm_reg_predictor #(spb_seq_item) spb2reg_predictor;    //Handle to the predictor


    //------------------------------------------------------------------------------------------------------
    //Automate frequently used methods, e.g get_full_name(), copy(), compare() etc.
    //Fields set here can be adapted higher in the environment hierarchy
    //------------------------------------------------------------------------------------------------------
    `uvm_component_utils (spb_environment)


    //------------------------------------------------------------------------------------------------------
    //Standard constructor for environment
    //------------------------------------------------------------------------------------------------------
    function new (string name = "spb_environment", uvm_component parent);
        super.new(name, parent);
    endfunction

The error that I receive is as follows:

class spb_environment extends uvm_env;
|
ncvlog: *E,NPITEM (…/vip/spb_uvc/sv/spb_environment.sv. 10|4): Not a valid package item: ‘module/udp instance’ [SystemVerilog]/
(include file : ....../vip/spb_uvc/sve/spb_top.sv line 10, include file: …/vip/spb_uvc/sv/spb_pkg.sv line 23, file : …/vip/spb_uvc/sve/spb_top.sv line 1)

I guess that this error is caused by the ordering of my `include macros, however, I cannot understand why I am getting such an error and how I would remove this error. Any suggestions would be much appreciate.

Regards,

Owen

In reply to owenjarvie:

Can you tell us what is in the preceding included file, spb_agent.sv ? I feel that may hold some clues.

In reply to Richard Hamer (EnSilica):

Richard,

The SPB agent is very simple. It builds and connects components as required depending on the active or passive bit set in the agent configuration. The code is shown below:

//------------------------------------------------------------------------------------------------------
//Start Of Class
//------------------------------------------------------------------------------------------------------
class spb_agent extends uvm_agent;


    //------------------------------------------------------------------------------------------------------
    //Class Data Members
    //------------------------------------------------------------------------------------------------------
    spb_monitor         spb_mon     ;       //Handle to SPB monitor
    spb_driver          spb_drv     ;       //Handle to SPB driver
    spb_sequencer       spb_sqr     ;       //Handle to SPB sequencer
    spb_agent_config    spb_ag_cfg  ;       //Handle to agent configuration
    
    virtual spb_if      spb_vif     ;       //Handle to virtual interface

    uvm_active_passive_enum spb_active;     //Controls whether SPB agent is active or passive, overwrite in config

    uvm_analysis_port #(spb_data_item) spb_ag_port;    //Agent Port
    

    //------------------------------------------------------------------------------------------------------
    //Automate frequently used methods, e.g get_full_name(), copy(), compare() etc.
    //Fields set here can be adapted higher in the environment hierarchy
    //------------------------------------------------------------------------------------------------------
    `uvm_component_utils_begin (spb_agent)
        //`uvm_field_object (spb_mon,     UVM_ALL_ON)
        //`uvm_field_object (spb_drv,     UVM_ALL_ON)
        //`uvm_field_object (spb_sqr,     UVM_ALL_ON)
        //`uvm_field_object (spb_ag_cfg,  UVM_ALL_ON)
        `uvm_field_enum (uvm_active_passive_enum, spb_active, UVM_ALL_ON)
    `uvm_component_utils_end


    //------------------------------------------------------------------------------------------------------
    //Standard constructor for agent
    //------------------------------------------------------------------------------------------------------
    function new (string name = "spb_agent", uvm_component parent);
        super.new(name, parent);
    endfunction


    //------------------------------------------------------------------------------------------------------
    //Build interface, agent configuration and agent components depending on whether agent is set to be 
    //active or passive.  Create agent port using the new() method
    //------------------------------------------------------------------------------------------------------
    function void build_phase (uvm_phase phase);
        super.build_phase (phase);

        //Create the agent port
        spb_ag_port = new("spb_ag_port", this);

        //Retrieve agent configuration from the database
        if (!uvm_config_db #(spb_agent_config)::get(this, "", "spb_agent_config", spb_ag_cfg)) begin
            `uvm_fatal ("AGT_CFG", "SPB Agent Config Not Found")
        end

        //Create config if it doesn't exist
        if (spb_ag_cfg == null) begin
            spb_ag_cfg = spb_agent_config::type_id::create("spb_agent_config", this);
        end

        //Retrieve interface from the database
        if (!uvm_config_db#(virtual spb_if)::get(this, "", "spb_vif", spb_vif)) begin
            `uvm_fatal ("AGT_NOVIF", "Could not get virtual interface from database.")
        end

        //Create a driver and a sequencer if agent is active
        if (spb_ag_cfg.spb_active == UVM_ACTIVE) begin
            spb_drv     = spb_driver::type_id::create("spb_drv", this);
            spb_sqr     = spb_sequencer::type_id::create("spb_sqr", this);
        end

        //Monitor created whether active or passive configuration
        spb_mon     = spb_monitor::type_id::create("spb_mon", this);
        `uvm_info ("SPB_AG_BUILD", "SPB Agent Build Phase Complete", UVM_LOW)

     endfunction : build_phase


    //------------------------------------------------------------------------------------------------------
    //Connect driver response port to sequencer if the agent is configured to require such a connection.
    //Connect driver port to the sequencer if the agent is in active configuration
    //------------------------------------------------------------------------------------------------------
    function void connect_phase (uvm_phase phase);
        super.connect_phase (phase);

        //If the spb agent is active connect the driver to the sequencer 
        if (spb_ag_cfg.spb_active == UVM_ACTIVE) begin
           //If the driver has to send a response back to sequencer
           if (spb_ag_cfg.spb_has_rsp != 0) begin
               spb_drv.rsp_port.connect(spb_sqr.rsp_export);
               `uvm_info ("SPB_AG_CONNECT", "Active SPB Agent Requires Response port", UVM_LOW)
           end
           //Connect driver to sequencer
           spb_drv.seq_item_port.connect(spb_sqr.seq_item_export);
           `uvm_info ("SPB_AG_CONNECT", "Active SPB Agent::Driver Connected to Sequencer", UVM_LOW)
        end
        else begin
            `uvm_info ("SPB_AG_CONNECT", "Passive SPB Agent::No Connections", UVM_LOW)
        end

    endfunction : connect_phase


endclass  spb_agent
//-----------------------------------------------
//End Of Class
//-----------------------------------------------

In reply to owenjarvie:

The last line should be:

endclass : spb_agent

You’re missing a “:”.

In reply to Tudor Timi:

Thanks Tudor Timi for pointing out my stupid mistake, much appreciated!