Compilation error for analysis fifo put method

UVM
1

Hi

I am calling put method for analysis fifo in my scoreboard task but having below compilation error
*E,NOTVFE : Expecting a SystemVerilog void function name. The task ‘put’ should be made a void function, not a task. Calling a task in this context is illegal SystemVerilog.

Same method is called in different scoreboard but error is not seen. Sometimes it is seen as warning.If anyone has any idea please help with error.

2

In reply to jaswanth_b:
The uvm_analysis_fifio has an analysis_export which provides a write function like this:

function void write (T t);

A put method is always blocking, but in the analysis path blocking ports cannot be used.

3

In reply to chr_sue:

Hi chr_sue,

Its working now,
But we have other version where it works with above mentioned put method. Now we are having issue with the same method in other version.

i have a doubt like : Did older version of UVM have this method and removed later ?
in Uvm reference there is a put method to write into analysis fifo.
Please clarify.

Thanks
Jaswanth.

4

In reply to jaswanth_b:

Yes in older UVM versions the put method was used. put is now used for blocking connections. The analysis path may not have blocking behavior. It has been refined to the write method.